1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly, to an apparatus and method for data-driving a liquid crystal display. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for reducing the number of data driver integrated circuits for driving data lines on a time-division basis.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) controls light transmittance of a liquid crystal using an electric field to display a picture. To this end, the LCD includes a liquid crystal display panel having liquid crystal cells arranged in an active matrix type, and a driving circuit for driving the liquid crystal display panel.
An LCD according to the related art, as shown in FIG. 1, includes data-driving IC's 4 connected through data tape carrier packages (TCP's) 6 to a liquid crystal display panel 2, and gate driving IC's 8 connected through gate TCP's 10 to the liquid crystal display panel 2.
More specifically, the liquid crystal display panel 2 includes a thin film transistor TFT formed at an intersection of a gate line and a data line, and a liquid crystal cell connected to the TFT. A gate electrode of the TFT is connected to one of the gate lines being vertical lines, and a source electrode is connected to one of the data lines being horizontal lines. Such a TFT responds to a scanning signal from the gate line to supply a pixel voltage signal from the data line to the liquid crystal cell. The liquid crystal cell includes a pixel electrode connected to a drain electrode of the TFT and a common electrode facing into the pixel electrode with a liquid crystal therebetween. Such a liquid crystal cell responds to the pixel voltage signal supplied to the pixel electrode to drive the liquid crystal, thereby controlling its light transmittance.
Each of the gate driving IC's 8 is mounted on the gate TCP 10. The gate driving IC's 8 mounted on the gate TCP 10 are electrically connected to the corresponding gate pads of the liquid crystal display panel 2 through the gate TCP 10. The gate driving IC's 8 sequentially drive the gate lines of the liquid crystal display panel 2 for each horizontal period 1H.
Each of the data-driving IC's 4 is mounted on the data TCP 6. The data-driving IC's 4 mounted on the data TCP 6 are electrically connected to the corresponding data pads of the liquid crystal display panel 2 through the data TCP 6. The data-driving IC's 4 convert digital pixel data into an analog pixel voltage signal and supply to the data lines of the liquid crystal display panel 2 for each horizontal period 1H.
To this end, as shown in FIG. 2, each of the data-driving IC's 4 includes a shift register 12 for applying a sequential sampling signal, first and second latch arrays 16 and 18 for latching and outputting a pixel data VD in response to the sampling signal, a first multiplexor MUX array 15 arranged between the first and second latch arrays 16 and 18, a digital-to-analog converter (DAC) array 20 for converting the pixel data from the second latch array 18 into a pixel voltage signal, a buffer array 26 for buffering and outputting the pixel voltage signal from the DAC array 20, and a second multiplexor array 30 for selecting a path of an output of the buffer array 26. Further, the data-driving IC 4 includes a data register 34 for interfacing pixel data (R, G, and B) from a timing controller (not shown), and a gamma voltage part 36 for supplying positive and negative gamma voltages required in the DAC array 20.
Each data-driving IC 4 having the configuration as mentioned above has n channel (e.g., 384 or 480 channel) data outputs to drive n data lines. FIG. 2 illustrates only 6 channels DL1 to DL6 of the n channels of the data-driving IC 4.
The data register 34 interfaces the pixel data from the timing controller and applies the pixel data to the first latch array 16. Particularly, the timing controller divides the pixel data into even pixel data RGBeven and odd pixel data RGBodd for the purpose of reducing a transmission frequency and supplies the divided pixel data through each transmission line to the data register 34. The data register 34 outputs the input even and odd pixel data RGBeven and RGBodd to the first latch array 16 over each transmission line. Herein, each of the even pixel data RGBeven and the odd pixel data RGBodd includes red(R), green(G), and blue(B) pixel data.
The gamma voltage part 36 further divides a plurality of gamma reference voltages from a gamma reference voltage generator (not shown) for each gray level and output the divided voltages.
The shift register array 12 generates a plurality of sequential sampling signals and applies the sampling signals to the first latch array 16. To this end, the shift register array 12 is comprised of n/6 shift registers 14. The shift register 14 at the first stage in FIG. 2 shifts a source start pulse SSP from the timing controller in response to a source sampling clock signal SSC to output the shifted source start pulse as a sampling signal. At the same time, the shift register 14 applies the sampling signal to the shift register 14 at the next stage as a carry signal CAR. The source start pulse SSP is applied for each horizontal period 1H, as shown in FIGS. 3A and 3B, and is shifted every source sampling clock signal SSC to be outputted as a sampling signal.
The first latch array 16 samples and latches the pixel data RGBeven and RGBodd from the data register 34 by a certain unit in response to the sampling signal from the shift register array 12. The first latch array 16 consists of n first latches 13 for latching n pixel data R, G, and B, each of which has a size corresponding to the bit number (i.e., 3 bits or 6 bits) of the pixel data R, G, and B. Such a first latch array 16 samples and latches the even pixel data RGBeven and the odd pixel data RGBodd (i.e., each 6 pixel data) for each sampling signal, and then outputs the latched data simultaneously.
The first multiplexor array 15 determines a path of the pixel data R, G, and B supplied from the first latch array 16 in response to a polarity control signal POL from the timing controller. To this end, the first multiplexor array 15 includes (n−1) first multiplexors 17. Each of the first multiplexors 17 receives output signals of the two adjacent first latches 13 to selectively output the signals in response to the polarity control signal POL. Herein, the outputs of the remaining first latches 13 excluding the first and last first latches 13 are commonly inputted to the two adjacent first multiplexors 17. The outputs of the first and last first latches 13 are commonly inputted to the second latch array 18 and the first multiplexor 17. The first multiplexor array 15 having the configuration as mentioned above allows the pixel data R, G, and B from each first latch 13 to be advanced into the second latch array 18 as they are, or to be progressed into the second latch array 18 with being shifted toward the right side by one position in response to the polarity control signal POL. The polarity control signal POL has a polarity inverted for each horizontal period 1H, as shown in FIGS. 3A and 3B. As a result, the first multiplexor array 15 allows each pixel data R, G, and B from the first latch array 16 to be outputted through the second latch array 18 to a positive (P) DAC 22 or a negative (N) DAC 24 of the DAC array 20 in response to the polarity control signal POL, thereby controlling the polarities of the pixel data R, G, and B.
The second latch array 18 simultaneously latches the inputted pixel data R, G, and B through the first multiplexor array 15, from the first latch array 16 in response to a source output enable signal SOE from the timing controller, and then output the latched pixel data. Particularly, the second latch array 18 includes (n+1) second latches 19 in consideration of the pixel data R, G, and B from the first latch array 16 inputted with being shifted to the right. The source output enable signal SOE is generated for each horizontal period 1H, as shown in FIGS. 3A and 3B. The second latch array 18 simultaneously latches the pixel data R, G, and B inputted at the rising edge of the source output enable signal SOE, and simultaneously outputs the latched pixel data at the falling edge thereof.
The DAC array 20 converts the pixel data R, G, and B from the second latch array 18 into pixel voltage signals with the aid of positive and negative gamma voltages GH and GL from the gamma voltage part 36 to output the pixel voltage signals. To this end, the DAC array 20 includes (n+1) PDAC's 22 and (n+1) NDAC's 24, which are alternately arranged in parallel to each other. The PDAC 22 converts the pixel data R, G, and B from the second latch array 18 into positive pixel voltage signals using the positive gamma voltages GH. On the other hand, the NDAC 24 converts the pixel data R, G, and B from the second latch array 18 into negative pixel voltage signals using the negative gamma voltages GL. Each of (n+1) buffers 28 is included in the buffer array 26 buffers and outputs a pixel voltage signal from each of the PDAC's 22 and the NDAC's 24 of the DAC array 20.
The second multiplexor array 30 determines a path of each pixel voltage signal from the buffer array 26 in response to the polarity control signal POL from the timing controller. To this end, the second multiplexor array 30 includes n second multiplexors 32. Each of the second multiplexors 32 selects any one output of the two adjacent buffers 28 in response to the polarity control signal POL and outputs the selected signal to the corresponding data line DL. Herein, the outputs of the remaining buffers 28 excluding the first and last buffers 28 are commonly inputted to the two adjacent second multiplexors. The second multiplexor array 30 having the configuration as mentioned above allows the pixel voltage signals from the buffers 28 excluding the last buffer 28 to be outputted to the data lines DL1 to DL6 as they are at a corresponding one to one relationship in response to the polarity control signal POL. Further, the second multiplexor array 30 allows the pixel voltage signals from the remaining buffers 28 excluding the first buffer 28 to be outputted to the data lines DL1 to DL6 with being shifted toward the left side by one position at a corresponding one to one relationship in response to the polarity control signal POL. The polarity control signal POL has a polarity inverted for each horizontal period 1H, as shown in FIGS. 3A and 3B, similar to the first multiplexor array 15. As mentioned above, the second multiplexor array 30, along with the first multiplexor array 15, determines polarities of the pixel voltage signals applied to the data lines DL1 to DL6 in response to the polarity control signal POL. As a result, the pixel voltage signal applied through the second multiplexor array 30 to each data line DL1 to DL6 has a polarity opposite to the adjacent pixel voltage signals. In other words, as shown in FIGS. 3A and 3B, the pixel voltage signals outputted to the odd data lines DLodd, such as DL1, DL3 and DL5, etc., have polarities opposite to the pixel voltage signals outputted to the even data lines DLeven, such as DL2, DL4 and DL6, etc. Polarities of the odd data lines DLodd and the even data lines DLeven are inverted for each horizontal period 1H at which the gate lines GL1, GL2, GL3, . . . are sequentially driven, and are inverted for each frame.
As described above, each of the related art data-driving IC's 4 requires (n+1) DAC's and (n+1) buffers so as to drive n data lines. As a result, the related art data-driving IC's 4 have disadvantages in that the configuration are complex and the manufacturing costs are relatively high.